FIG. 1 shows a block diagram of a conventional phase-locked loop.
As shown in FIG. 1, the phase-locked loop has a phase detector 101, a charge pump 103, a loop filter 105, and a voltage controlled oscillator 107. The voltage controlled oscillator 107 controls frequency of an outputted oscillation signal CLK, according to an inputted voltage signal. The phase detector 101 outputs UP and DOWN signals when the frequency of the oscillation signal CLK outputted from the voltage controlled oscillator 107 is not matched with that of a reference oscillation signal REFCLK. More specifically, the phase detector outputs the UP signal if the frequency of the oscillation signal CLK is less than that of the reference oscillation signal REFCLK, and outputs the DN signal if the frequency of the oscillation signal CLK is greater than that of the reference oscillation signal REFCLK. The charge pump 203 outputs positive current pulse in case that an applied voltage pulse is the UP signal, and outputs negative current pulse in case that the applied voltage pulse is the DN signal. Generally, the loop filter 105 comprises a large capacitor, and controls an output voltage VCLT by adding charge to the capasitor or removing charge from the capacitor in accordance with the inputted current pulse. The voltage controlled oscillator 107 controls the frequency of the oscillation signal CLK by the voltage Vclt outputted from the loop filter 105. That is, the frequency of the oscillation signal CLK is increased when the output voltage Vclt of the loop filter 105 is raised, and the frequency of the oscillation signal CLK is decreased when the output voltage VCLT of the loop filter 105 is gone down.
Accordingly, when the frequency of the oscillation signal CLK which is outputted from the voltage controlled oscillator 107 is less than the reference oscillation signal REFCLK, the phase detector 101 generates the UP signal, and the charge pump 103 charges the capacitor of the loop filter 105 by outputting the positive current pulse. Moreover, the voltage Vclt applied to the voltage controlled oscillator 107 is raised, and the frequency of the oscillation signal CLK is increased. On the other hands, when the frequency of the oscillation signal CLK which is outputted from the voltage controlled oscillator 107 is greater than the reference oscillation signal REFCLK, the phase detector 101 generates the DN signal, and the voltage VCLT applied to the voltage controlled oscillator 107 is gone down, and the frequency of the oscillation signal CLK is decreased.
FIG. 2 shows a circuit diagram of conventional charge pump used in the phase locked loop shown in FIG. 1.
As shown in FIG. 2, the conventional charge pump 103 comprises the first and second PMOS transistors MP21, MP22, and the first and second NMOS transistors MN21, MN22. The first PMOS and NMOS transistors MP21, MN21 are implemented by common-source transistors, and activated or inactivated by voltage pulses UPB, DN which are applied to gates thereof, respectively. The second PMOS and NMOS transistors MP22, MN22 are implemented by common-gate transistors, and constant bias voltages BIASP, BIASN are applied to gates, respectively.
Below, operation and problems of the conventional charge pump 103 are illustrated, with referring to FIG. 2.
When the UP pulse of the phase detector 101 is pulsed high, the UPB pulse of the charge pump 103 is pulsed low. Accordingly, the first PMOS transistor MP21 is activated. Tthe source of the second PMOS transistor MP22 is charged, and source voltage is raised until the gate-to-source voltage exceeds the threshold voltage. Accordingly, a source current Isource flows from voltage source to the first and second PMOS transistors MP21, MP22, and the capacitor C21 connected to the output terminal VLFO is charged.
When the DN pulses is pulses high, the first NMOS transistor MN21 is activated. The source of the second NMOS transistor MN21 is discharged, and source voltage is gone down until the gate-to-source voltage exceeds the threshold voltage. Accordingly, a sink current Isink flows from the output terminal a charge pump circuit to the ground through the first and second NMOS transistors MN21, MN22, and the capacitor C21 is discharged.
In the conventional charge pump circuit 103, amounts of the source and sink currents Isource, Isink flowing to the output terminal VLFO is controlled by the bias voltages BIASP, BIASN which is applied to the gates of the second PMOS and NMOS transistors MP22, MN22. Generally, the bias voltages BIASP, BIASN is setted to predetermined voltages so that amounts of the source and the sink currents Isource, Isink are same.
However, a parasitic capacitance generated between gate and source of the second NMOS transistor MN22 drops quickly gate voltage of the second NMOS transistor MN22 which controls the sink current Isink when the DN signal is applied. Accordingly, the sink current Isink flowing the output terminal VLFO is not desired current. Although, voltage drop by parasitic capacitance is corrected by the biasing unit 2100, in the conventional charge pump circuit, correction time is needed. Moreover, parasitic capacitance generated from the source of the second NMOS transistor MN22 delays voltage drop of the source terminal to the ground and prevents a desired sink current Isink from flowing to the output terminal VLFO.
On the other hand, the gate voltage of the second PMOS transistor MP22 is raised quickly by parasitic capacitance generated between gate and source of the second PMOS transistor MP22 when the UP signal is applied. Moreover, parasitic capacitance generated from the source of the second PMOS transistor MP22 delays voltage rise of source terminal to value of the voltage source, and prevents a desired source current Isource from flowing to the output terminal VLFO.
Accordingly, the conventional charge pump circuit has problems that switching speed is low, and current mismatch generated between source and sink currents during current switching owing to parasitic capacitance. This current mismatch generates spurious tone, and deteriorates the phase noise figure of the phase-locked loop.
In order to resolve above problems, in conventional charge pump circuit 103, there are the method that increases impedance by being long the length of the first and second NMOS transistor MN21, MN22 used to CMOS charge pump, and the method that has greater impedance than general circuit by the second NMOS and PMOS transistor MN22, MP22 consisted of cascode. But, in case being long the length of element, swiching speed is slow, and in case that element is consisted of cascode, operating range of a charge pump is small. Moreover, because a output impedance can not substantially become in infinity, they have a limit in that source and sink currents is harmonized.